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a
+2.5 V to +5.5 V, 230 A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs AD5303/AD5313/AD5323*
GENERAL DESCRIPTION
FEATURES AD5303: Two Buffered 8-Bit DACs in One Package AD5313: Two Buffered 10-Bit DACs in One Package AD5323: Two Buffered 12-Bit DACs in One Package 16-Lead TSSOP Package Micropower Operation: 300 A @ 5 V (Including Reference Current) Power-Down to 200 nA @ 5 V, 50 nA @ 3 V +2.5 V to +5.5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic By Design Over All Codes Buffered/Unbuffered Reference Input Options Output Range: 0-VREF or 0-2 V REF Power-On-Reset to Zero Volts SDO Daisy-Chaining Option Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Rail-to-Rail Output Buffer Amplifiers APPLICATIONS Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators
The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit buffered voltage output DACs in a 16-lead TSSOP package that operate from a single +2.5 V to +5.5 V supply consuming 230 A at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/s. The AD5303/ AD5313/AD5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPITM, QSPI, MICROWIRETM and DSP interface standards. The references for the two DACs are derived from two reference pins (one per DAC). These reference inputs may be configured as buffered or unbuffered inputs. The parts incorporate a poweron-reset circuit that ensures that the DAC outputs power-up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears both DACs to 0 V. The outputs of both DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and provides software-selectable output loads while in power-down mode. The parts may also be used in daisy-chaining applications using the SDO pin. The low power consumption of these parts in normal operation make them ideally suited to portable battery operated equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V, reducing to 1 W in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD BUF A VREFA
POWER-ON RESET INPUT REGISTER SYNC SCLK DIN INPUT REGISTER DAC REGISTER STRING DAC INTERFACE LOGIC DAC REGISTER STRING DAC
AD5303/AD5313/AD5323
BUFFER
VOUTA
>
POWER-DOWN LOGIC
RESISTOR NETWORK
BUFFER
VOUTB
SDO
GAIN-SELECT LOGIC
RESISTOR NETWORK
DCEN
LDAC CLR
PD
BUF B
VREFB
GND
*Protected by U.S. Patent No. 5684481; other patents pending. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD5303/AD5313/AD5323-SPECIFICATIONS
(VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k
Parameter1 DC PERFORMANCE AD5303 Resolution Relative Accuracy Differential Nonlinearity AD5313 Resolution Relative Accuracy Differential Nonlinearity AD5323 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband Offset Error Drift5 Gain Error Drift5 Power Supply Rejection Ratio5 DC Crosstalk5 DAC REFERENCE INPUTS5 VREF Input Range VREF Input Impedance 1 0 >10 180 90 Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 Maximum Output Voltage6 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS5 Input Current VIL, Input Low Voltage -90 -80 0.001 VDD - 0.001 0.5 50 20 2.5 5 1 0.8 0.6 0.5 2.4 2.1 2.0 2
5 3, 4
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
B Version2 Typ Max Units Conditions/Comments
Min
8 0.15 0.02 10 0.5 0.05 12 2 0.2 0.4 0.15 10 -12 -5 -60 30
1 0.25 3 0.5 12 1 3 1 60
Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FSR % of FSR mV ppm of FSR/C ppm of FSR/C dB V V V M k k dB dB V min V max mA mA s s A V V V V V V pF
Guaranteed Monotonic by Design Over All Codes
Guaranteed Monotonic by Design Over All Codes
Guaranteed Monotonic by Design Over All Codes See Figures 3 and 4 See Figures 3 and 4 See Figures 3 and 4 VDD = 10%
VDD VDD
Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode Unbuffered Reference Mode. 0-VREF Output Range, Input Impedance = RDAC Unbuffered Reference Mode. 0-2 VREF Output Range, Input Impedance = RDAC Frequency = 10 kHz Frequency = 10 kHz
This is a measure of the minimum and maximum drive capability of the output amplifier.
VDD = +5 V VDD = +3 V Coming Out of Power-Down Mode. VDD = +5 V Coming Out of Power-Down Mode. VDD = +3 V
VIH, Input High Voltage
VDD = +5 V VDD = +3 V VDD = +2.5 V VDD = +5 V VDD = +3 V VDD = +2.5 V
10% 10% 10% 10%
Pin Capacitance LOGIC OUTPUT (SDO) VDD = +5 V 10% Output Low Voltage Output High Voltage VDD = +3 V 10% Output Low Voltage Output High Voltage Floating-State Leakage Current Floating State O/P Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = +4.5 V to +5.5 V VDD = +2.5 V to +3.6 V
3.5
0.4 4.0 0.4 2.4 1 3
V V V V A pF
ISINK = 2 mA ISOURCE = 2 mA ISINK = 2 mA ISOURCE = 2 mA DCEN = GND DCEN = GND
2.5 300 230
5.5 450 350
V A A A A
IDD Specification Is Valid for All DAC Codes Both DACs Active and Excluding Load Currents Both DACs in Unbuffered Mode. VIH = VDD and VIL = GND. In Buffered Mode, extra current is typically x A per DAC where x = 5 A + VREF/RDAC.
IDD (Full Power-Down) VDD = +4.5 V to +5.5 V VDD = +2.5 V to +3.6 V
0.2 0.05
1 1
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NOTES 1 See Terminology. 2 Temperature range: B Version: -40C to +105C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and "Offset plus Gain" Error must be positive. Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter
2
(VDD = +2.5 V to +5.5 V; RL = 2 k otherwise noted.)
B Version3 Min Typ Max
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
Units
Conditions/Comments
Output Voltage Settling Time AD5303 AD5313 AD5323 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
6 7 8 0.7 12 0.10 0.01 0.01 200 -70
8 9 10
s s s V/s nV-s nV-s nV-s nV-s kHz dB
VREF = VDD = +5 V 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex) 1 LSB Change Around Major Carry (011 . . . 11 to 100 . . . 00)
VREF = 2 V 0.1 V p-p. Unbuffered Mode VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz
NOTES 1 Guaranteed by design and characterization, not production tested. 2 See Terminology. 3 Temperature range: B Version: -40C to +105C. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3 (V
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t124, 5 t134, 5 t145 t155 Limit at TMIN, TMAX (B Version) 33 13 13 0 5 4.5 0 100 20 20 20 5 20 0 10
DD
= +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted.)
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time LDAC Pulsewidth SCLK Falling Edge to LDAC Rising Edge CLR Pulsewidth SCLK Falling Edge to SDO Invalid SCLK Falling Edge to SDO Valid SCLK Falling Edge to SYNC Rising Edge SYNC Rising Edge to SCLK Rising Edge
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 See Figures 1 and 2. 4 These are measured with the load circuit of Figure 1. 5 Daisy-Chain Mode only (see Figure 45). Specifications subject to change without notice.
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AD5303/AD5313/AD5323
2mA TO OUTPUT PIN IOL
+1.6V CL 50pF 2mA IOH
Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications
t1 SCLK t8 SYNC t6 t5 DIN* DB15 DB0 t9 LDAC t10 LDAC t11 CLR *SEE PAGE 12 FOR DESCRIPTION OF INPUT REGISTER t3 t4 t2 t7
Figure 2. Serial Interface Timing Diagram
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ABSOLUTE MAXIMUM RATINGS 1, 2 PIN CONFIGURATION
(TA = +25C unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . -0.3 V to VDD + 0.3 V VOUTA, VOUTB to GND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . +150C 16-Lead TSSOP Package Power Dissipation . . . . . . . . . . . . . . . . . . (TJ Max - TA)/JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
CLR 1 LDAC 2 VDD 3 VREFB 4
16 SDO 15 GND
AD5303/ AD5313/ AD5323
TOP VIEW
14 DIN 13 SCLK
VREFA 5 (Not to Scale) 12 SYNC VOUTA 6 BUF A 7 BUF B 8
11 VOUTB 10 PD 9
DCEN
ORDERING GUIDE
Model AD5303BRU AD5313BRU AD5323BRU
Temperature Range -40C to +105C -40C to +105C -40C to +105C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option RU-16 RU-16 RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD5303/AD5313/AD5323
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2
Mnemonic CLR LDAC
Function Active low control input that loads all zeroes to both input and DAC registers. Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows simultaneous update of both DAC outputs Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be decoupled to GND. Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Control pin that controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. Control pin that controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy-chain. The pin should be tied low if it is being used in stand-alone mode. Active low control input that acts as a hardware power-down option. This pin overrides any software power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers-on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered-down after each write cycle. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered-down after each write cycle. Ground reference point for all circuitry on the part. Serial Data Output that can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.
3 4
VDD VREFB
5
VREFA
6 7 8 9 10
VOUTA BUF A BUF B DCEN PD
11 12
VOUTB SYNC
13
SCLK
14 15 16
DIN GND SDO
TERMINOLOGY
RELATIVE ACCURACY
OFFSET ERROR
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 5.
DIFFERENTIAL NONLINEARITY
This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8.
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. -6- REV. 0
AD5303/AD5313/AD5323
MAJOR-CODE TRANSITION GLITCH ENERGY MULTIPLYING BANDWIDTH
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
CHANNEL-TO-CHANNEL ISOLATION
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa.
ANALOG CROSSTALK
This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of the other DAC. It is measured in dBs.
GAIN ERROR PLUS OFFSET ERROR IDEAL OUTPUT VOLTAGE ACTUAL
This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-secs.
DAC-TO-DAC CROSSTALK
NEGATIVE OFFSET ERROR
DAC CODE
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of the other DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC low and monitoring the output of the other DAC. The area of the glitch is expressed in nV-secs.
DC CROSSTALK
AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR
DEADBAND
This is the dc change in the output level of one DAC in response to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while monitoring the other DAC. It is expressed in V.
POWER SUPPLY REJECTION RATIO (PSRR)
Figure 3. Transfer Function with Negative Offset
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at +2 V and VDD is varied 10%.
REFERENCE FEEDTHROUGH
GAIN ERROR PLUS OFFSET ERROR ACTUAL OUTPUT VOLTAGE
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.
TOTAL HARMONIC DISTORTION
IDEAL POSITIVE OFFSET ERROR
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.
DAC CODE
Figure 4. Transfer Function with Positive Offset
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AD5303/AD5313/AD5323-Typical Performance Characteristics
1.0 TA = +25 C VDD = +5V
3 2 TA = +25 C VDD = +5V
12 TA = +25 C VDD = +5V
8 INL ERROR - LSBs
0
INL ERROR - LSBs
INL ERROR - LSBs
0.5
1
4 0
0
0
-1
-4
-0.5
-2
-8 -12
200 400 600 CODE 800 1000
-1.0
0
50
100
150 CODE
200
250
-3
0
1000
2000 CODE
3000
4000
Figure 5. AD5303 Typical INL Plot
Figure 6. AD5313 Typical INL Plot
Figure 7. AD5323 Typical INL Plot
0.3 TA = +25 C VDD = +5V
0.6
0.2
TA = +25 C VDD = +5V
1.0 TA = +25 C VDD = +5V
DNL ERROR - LSBs
0.4
DNL ERROR - LSBs
0.1
DNL ERROR - LSBs
0.5
0.2
0
0
0
-0.1
-0.2 -0.4 -0.6 0 200 400 600 CODE 800 1000
-0.5 -0.2
-0.3
0
50
100 150 CODE
200
250
-1
0
1000
2000 CODE
3000
4000
Figure 8. AD5303 Typical DNL Plot
Figure 9. AD5313 Typical DNL Plot
Figure 10. AD5323 Typical DNL Plot
1.00 0.75 0.50 VDD = +5V TA = +25 C
1.00 0.75 0.50 VDD = +5V VREF = +3V
1.0 VDD = +5V VREF = +2V 0.5 MAX DNL MAX INL
ERROR - LSBs
ERROR - LSBs
0.00 -0.25 -0.50 -0.75 -1.00
MAX INL MAX DNL MIN DNL MIN INL
0 -0.25 MIN INL -0.50 -0.75 -1.00 -40 MIN DNL
ERROR - %
0.25
0.25
GAIN ERROR 0.0
OFFSET ERROR -0.5
2
3 VREF - V
4
5
0
40 80 TEMPERATURE - C
120
-1.0 -40
0
40 80 TEMPERATURE - C
120
Figure 11. AD5303 INL and DNL Error vs. VREF
Figure 12. AD5303 INL Error and DNL Error vs. Temperature
Figure 13. Offset Error and Gain Error vs. Temperature
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5 5V SOURCE VDD = +5V VDD = +3V 4
600
TA = +25 C VDD = +5V
500 400
IDD - A
6
FREQUENCY
VOUT - Volts
3
3V SOURCE
300
2
200
1 5V SINK 0 100 0 3V SINK
100 0
150
200
250 300 IDD - A
350
400
0
2 3 4 5 1 SINK/SOURCE CURRENT - mA
ZERO-SCALE
FULL-SCALE
Figure 14. IDD Histogram with VDD = +3 V and VDD = +5 V
Figure 15. Source and Sink Current Capability
Figure 16. Supply Current vs. Code
600 BOTH DACS IN GAIN-OF-TWO MODE REFERENCE INPUTS BUFFERED 500 400
1.0 0.9 0.8 0.7
IDD - A
A
700
BOTH DACS IN THREE-STATE CONDITION
600 500 400
TA = +25 C
IDD - A
-40 C 300 +105 C 200
+25 C
0.6 0.5 0.4 0.3 -40 C 0.2 0.1 +25 C +105 C
IDD -
VDD = +5V 300 200 100 VDD = +3V
100
0 2.5
3
3.5
4 4.5 VDD - Volts
5
5.5
0 2.7
3.2
3.7 4.2 VDD - Volts
4.7
5.2
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VLOGIC - Volts
Figure 17. Supply Current vs. Supply Voltage
Figure 18. Power-Down Current vs. Supply Voltage
Figure 19. Supply Current vs. Logic Input Voltage
VDD = +5V TA = +25 C CH2 CLK
TA = +25 C VDD
TA = +25 C
CH1
VOUT
CH1 CH2 VOUTA
CH1
CH3
CLK
CH1 1V, CH2 5V, TIME BASE = 5 s/DIV
CH1 1V, CH2 1V, TIME BASE = 20 s/DIV
CH1 1V, CH3 5V, TIME BASE = 1 s/DIV
Figure 20. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 21. Power-On Reset to 0 V
Figure 22. Exiting Power-Down to Midscale
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2.50
10 0 -10
VOUT - Volts
2.49
-20
dB
-30
2.48
-40 -50
2.47 1 s/DIV
-60 0.01
0.1
1 10 100 FREQUENCY - kHz
1k
10k
2mV/DIV
500ns/DIV
Figure 23. AD5323 Major-Code Transition
Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)
Figure 25. DAC-DAC Crosstalk
0.10 VDD = +5V TA = +25 C
FULL-SCALE ERROR - Volts
0.05
0.00
-0.05
-0.10
0
1
2 3 VREF - Volts
4
5
Figure 26. Full-Scale Error vs. VREF (Buffered)
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FUNCTIONAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10 and 12 bits respectively. They contain reference buffers, output buffer amplifiers and are written to via a 3-wire serial interface. They operate from single supplies of +2.5 V to +5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/s. Each DAC is provided with a separate reference input, which may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from GND to VDD. The devices have three programmable power-down modes, in which one or both DACs may be turned off completely with a high-impedance output, or the output may be pulled low by an on-chip resistor.
Digital-to-Analog Section
R R R TO OUTPUT AMPLIFIER
R R
Figure 28. Resistor String
DAC Reference Inputs
The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 27 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:
VOUT = VREF x D 2N
There is a reference input pin for each of the two DACs. The reference inputs are buffered but can also be configured as unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as GND and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier. If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5303/AD5313/ AD5323. In unbuffered mode the input impedance is still large at typically 180 k per reference input for 0-VREF mode and 90 k for 0-2 VREF mode. The buffered/unbuffered option is controlled by the BUF A and BUF B pins. If the BUF pin is tied high, the reference input is buffered, if tied low, it is unbuffered.
Output Amplifier
where D = decimal equivalent of the binary code, which is loaded to the DAC register; 0-255 for AD5303 (8 Bits) 0-1023 for AD5313 (10 Bits) 0-4095 for AD5323 (12 Bits) N = DAC resolution
VREFA
REFERENCE BUFFER
BUF A
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail which gives an output range of 0.001 V to VDD - 0.001 V when the reference is VDD. It is capable of driving a load of 2 k in parallel with 500 pF to GND and VDD. The source and sink capabilities of the output amplifier can be seen in Figure 15.
VOUTA
The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at 8 bits) of 6 s.
POWER-ON RESET
Figure 27. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
The AD5303/AD5313/AD5323 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is: - Normal operation. - 0-VREF output range. - Output voltage set to 0 V. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
Clear Function (CLR)
The CLR pin is an active low input which, when pulled low, loads all zeros to both input registers and both DAC registers. This enables both analog outputs to be cleared to 0 V.
REV. 0
-11-
AD5303/AD5313/AD5323
SERIAL INTERFACE
The AD5303/AD5313/AD5323 are controlled over a versatile, 3-wire serial interface, which operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE and DSP interface standards.
Input Shift Register
SYNC may be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer will be aborted and the input registers will not be updated. When data has been transferred into both input registers, the DAC registers of both DACs may be simultaneously updated, by taking LDAC low. CLR is an active-low, asynchronous clear that clears the input and DAC registers of both DACs to all zeroes.
Low Power Serial Interface
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. The 16-bit word consists of four control bits followed by 8, 10 or 12 bits of DAC data, depending on the device type. The first bit loaded is the MSB (Bit 15), which determines whether the data is for DAC A or DAC B. Bit 14 determines the output range (0-VREF or 0-2 VREF). Bits 13 and 12 control the operating mode of the DAC.
Table I. Control Bits
Bit 15 14 13 12
Name A/B GAIN PD1 PD0
Function 0: Data Written to DAC A 1: Data Written to DAC B 0: Output Range of 0-VREF 1: Output Range of 0-2 VREF Mode Bit Mode Bit
Power-On Default N/A 0 0 0
To reduce the power consumption of the device even further, the interface only powers up fully when the device is being written to. As soon as the 16-bit control word has been written to the part, the SCLK and DIN input buffers are powered-down. They only power-up again following a falling edge of SYNC.
Double-Buffered Interface
The AD5303/AD5313/AD5323 DACs all have double-buffered interfaces consisting of two banks of registers--input registers and DAC registers. The input register is connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. This is useful if the user requires simultaneous updating of both DAC outputs. The user may write to both input registers individually and then, by pulsing the LDAC input low, both outputs will update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the
The remaining bits are DAC data bits, starting with the MSB and ending with the LSB. The AD5323 uses all 12 bits of DAC data, the AD5313 uses 10 bits and ignores the two LSBs. The AD5303 uses eight bits and ignores the last four bits. The data format is straight binary, with all zeroes corresponding to 0 V output, and all ones corresponding to full-scale output (VREF - 1 LSB). The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC to SCLK active edge setup time, t4. After SYNC goes low, serial data will be shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. Any data and clock pulses after the 16th will be ignored, and no further serial data transfer will occur until SYNC is taken high and low again.
DB15 (MSB) A/B GAIN PD1 PD0 D7 D6 D5 D4
DB0 (LSB) D3 D2 D1 D0 X X X X
DATA BITS
Figure 29. AD5303 Input Shift Register Contents
DB15 (MSB) A/B GAIN PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB0 (LSB) X X
DATA BITS
Figure 30. AD5313 Input Shift Register Contents
DB15 (MSB) A/B GAIN PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DB0 (LSB) D1 D0
DATA BITS
Figure 31. AD5323 Input Shift Register Contents
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REV. 0
AD5303/AD5313/AD5323
contents of the input registers. In the case of the AD5303/AD5313/ AD5323, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated thereby removing unnecessary digital crosstalk.
POWER-DOWN MODES MICROPROCESSOR INTERFACING AD5303/AD5313/AD5323 to ADSP-2101/ADSP-2103 Interface
The AD5303/AD5313/AD5323 have very low power consumption, dissipating only 0.7 mW with a 3 V supply and 1.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bits 13 and 12 (PD1 and PD0) of the control word. Table II shows how the state of the bits corresponds to the mode of operation of that particular DAC.
Table II. PD1/PD0 Operating Modes
Figure 33 shows a serial interface between the AD5303/AD5313/ AD5323 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active-Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
ADSP-2101/ ADSP-2103* TFS DT
SYNC AD5323* DIN SCLK
AD5303/ AD5313/
PD1 0 0 1 1
PD0 0 1 0 1
Operating Mode
SCLK
Normal Operation Power-Down (1 k Load to GND) Power-Down (100 k Load to GND) Power-Down (High Impedance Output)
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5303/AD5313/AD5323 to ADSP-2101/ADSP2103 Interface
AD5303/AD5313/AD5323 to 68HC11/68L11 Interface
When both bits are set to 0, the DACs work normally with their normal power consumption of 300 A at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V) when both DACs are powered down. Not only does the supply current drop but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in powerdown mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different options. The output is connected internally to GND through a 1 k resistor, a 100 k resistor or it is left in a high impedance state (Three-State). The output stage is illustrated in Figure 32. The bias generator, the output amplifier, the resistor string and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V. See Figure 22 for a plot. The software power-down modes programmed by PD0 and PD1 are overridden by the PD pin. Taking this pin low puts both DACs into power-down mode simultaneously and both outputs are put into a high impedance state. If PD is not used it should be tied high.
Figure 34 shows a serial interface between the AD5303/AD5313/ AD5323 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5303/AD5313/ AD5323, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data to the AD5303/AD5313/AD5323, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC and PC7 is taken high at the end of this procedure.
68HC11/68L11* PC7 SCK
SYNC AD5323* SCLK DIN
AD5303/ AD5313/
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY. RESISTOR STRING DAC AMPLIFIER VOUT
Figure 34. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface
POWER-DOWN CIRCUITRY
RESISTOR NETWORK
Figure 32. Output Stage During Power-Down
REV. 0
-13-
AD5303/AD5313/AD5323
AD5303/AD5313/AD5323 to 80C51/80L51 Interface
Figure 35 shows a serial interface between the AD5303/AD5313/ AD5323 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TXD of the 80C51/80L51 drives SCLK of the AD5303/AD5313/AD5323, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case port line P3.3 is used. When data is to be transmitted to the AD5303/ AD5313/AD5323, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 outputs the serial data in a format that has the LSB first. The AD5303/AD5313/AD5323 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51* P3.3 TXD
reference buffers are used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the REF191, a 2.048 V reference.
VDD = +2.5V TO +5.5V
EXT V OUT REF
VDD 1F VREFA VREFB VOUTA
AD780/REF192 WITH VDD = +5V OR REF191 WITH VDD = +2.5V
AD5303/ AD5313/ AD5323
SCLK DIN SYNC VOUTB
GND BUF A BUF B SERIAL INTERFACE
Figure 37. AD5303/AD5313/AD5323 Using External Reference
SYNC AD5323* SCLK DIN
AD5303/ AD5313/
RXD
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5303/AD5313/AD5323 to 80C51/80L51 Interface
AD5303/AD5313/AD5323 to MICROWIRE Interface
Figure 36 shows an interface between the AD5303/AD5313/ AD5323 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5303/AD5313/AD5323 on the rising edge of the SK.
MICROWIRE* CS SK
If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered (for example 0 V to +5 V) then the simplest solution is to connect the reference inputs to VDD. As this supply may not be very accurate and may be noisy, then the AD5303/AD5313/AD5323 may be powered from the reference voltage, for example using a 5 V reference such as the REF195, as shown in Figure 38. The REF195 will output a steady supply voltage for the AD5303/AD5313/AD5323. The current required from the REF195 is 300 A supply current and approximately 30 A or 60 A into each of the reference inputs (if unbuffered). This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 k load on each output) is: 360 A + 2 (5 V/10 k) = 1.36 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 2.7 ppm (13.5 V) for the 1.36 mA current drawn from it. This corresponds to a 0.0007 LSB error at 8 bits and 0.011 LSB error at 12 bits.
+15V
AD5303/ AD5313/ SYNC AD5323*
SCLK DIN
SO
VIN
0.1 F
10 F
*ADDITIONAL PINS OMITTED FOR CLARITY.
REF195 VOUT GND 1F
VDD VREFA VREFB VOUTA
Figure 36. AD5303/AD5313/AD5323 to MICROWIRE Interface
APPLICATIONS INFORMATION Typical Application Circuit
AD5303/ AD5313/ AD5323
SCLK DIN SYNC VOUTB
The AD5303/AD5313/AD5323 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, the AD5303/AD5313/AD5323 may be used with a fixed, precision reference voltage. Figure 37 shows a typical setup for the AD5303/AD5313/AD5323 when using an external reference. If the reference inputs are unbuffered, the reference input range is from 0 V to VDD, but if the on-chip
GND BUF A BUF B SERIAL INTERFACE
Figure 38. Using an REF195 as Power and Reference to the AD5303/AD5313/AD5323
-14-
REV. 0
AD5303/AD5313/AD5323
Bipolar Operation Using the AD5303/AD5313/AD5323
The AD5303/AD5313/AD5323 has been designed for single supply operation, but bipolar operation is also achievable using the circuit shown in Figure 39. The circuit shown has been configured to achieve an output voltage range of -5 V < VOUT < +5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier.
+6V TO +16V VDD = +5V R2 10k +5V R1 10k VIN REF195 VOUT GND 1F VDD VREFA/B AD820/ OP295 -5V 5V
POWER
+5V REGULATOR
10 F
0.1 F
VDD 10k SCLK SCLK VDD VREFA VREFB VDD 10k SYNC SYNC VOUTA VOUTB VDD 10k DIN DIN GND BUF A BUF B
0.1 F
10 F
AD5303/ AD5313/ AD5323
AD5303/ AD5313/ AD5323
SCLK DIN SYNC GND BUF A BUF B VOUTA/B
SERIAL INTERFACE
Figure 40. AD5303/AD5313/AD5323 in an Opto-Isolated Interface
Decoding Multiple AD5303/AD5313/AD5323s
Figure 39. Bipolar Operation Using the AD5303/AD5313/ AD5323
The output voltage for any input code can be calculated as follows: VOUT = [(VREF x D/2N) x (R1+R2)/R1 - VREF x (R2/R1)] where: D is the decimal equivalent of the code loaded to the DAC and N is the DAC resolution. VREF is the reference voltage input, and gain bit = 0. with: VREF = 5 V R1 = R2 = 10 k and VDD = 5 V VOUT = (10 x D/2N) - 5 V
Opto-Isolated Interface for Process Control Applications
The SYNC pin on the AD5303/AD5313/AD5323 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices will be active at any one time, allowing access to two channels in this 8-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 41 shows a diagram of a typical setup for decoding multiple AD5303/AD5313/AD5323 devices in a system.
SCLK DIN VDD VCC ENABLE CODED ADDRESS 1G 1A 1B 1Y0 1Y1 74HC139 1Y2 1Y3 DGND SYNC DIN SCLK SYNC DIN SCLK SYNC DIN SCLK
AD5303/ AD5313/ AD5323
The AD5303/AD5313/AD5323 has a versatile 3-wire serial interface making it ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements or distance, it may be necessary to isolate the AD5303/AD5313/AD5323 from the controller. This can easily be achieved by using opto-isolators, which will provide isolation in excess of 3 kV. The serial loading structure of the AD5303/ AD5313/AD5323 makes it ideally suited for use in opto-isolated applications. Figure 40 shows an opto-isolated interface to the AD5303/AD5313/AD5323 where DIN, SCLK and SYNC are driven from opto-couplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a +5 V regulator provides the +5 V supply required for the AD5303/AD5313/AD5323.
AD5303/ AD5313/ AD5323
AD5303/ AD5313/ AD5323
SYNC DIN SCLK
AD5303/ AD5313/ AD5323
Figure 41. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System
REV. 0
-15-
AD5303/AD5313/AD5323
AD5303/AD5313/AD5323 as a Digitally Programmable Window Detector Daisy-Chain Mode
A digitally programmable upper/lower limit detector using the two DACs in the AD5303/AD5313/AD5323 is shown in Figure 42. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, a LED will indicate the fail condition.
+5V 0.1 F 10 F VIN VDD VOUTA 1/2 CMP04 PASS/FAIL 1k FAIL 1k PASS
This mode is used for updating serially-connected or standalone devices on the rising edge of SYNC. For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin may be used to daisy-chain several devices together and provide serial readback. By connecting DCEN (Daisy-Chain Enable) pin high, the Daisy-Chain Mode is enabled. It is tied low in the case of Stand-Alone Mode. In Daisy-Chain Mode the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out after the falling edge of SCLK and is valid on the subsequent rising and falling edges. By connecting this line to the DIN input on the next DAC in the chain, a multiDAC interface is constructed. Sixteen clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers and all analog outputs are updated simultaneously.
68HC11* MOSI SCK PC7 PC6 DIN SCLK SYNC LDAC SDO
VREF
VREFA VREFB
AD5303/ AD5313/ AD5323
SYNC DIN SCLK SYNC DIN SCLK GND VOUTB
1/6 74HC05
Figure 42. Window Detector Using AD5303/AD5313/AD5323
Coarse and Fine Adjustment Using the AD5303/AD5313/ AD5323
The DACs in the AD5303/AD5313/AD5323 can be paired together to form a coarse and fine adjustment function, as shown in Figure 43. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments. With the resistor values and external reference shown, the output amplifier has unity gain for the DAC A output, so the output range is 0 V to 2.5 V - 1 LSB. For DAC B the amplifier has a gain of 7.6 x 10-3, giving DAC B a range equal to 19 mV. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a rail-to-rail output swing.
VDD = +5V R3 51.2k R4 390 +5V
AD5303/ AD5313/ AD5323*
(DAC 1)
MISO
0.1 F
10 F
DIN
VIN EXT V OUT REF GND
VDD VREFA 1F VOUTA R1 390 AD820/ OP295
VOUT
AD5303/ AD5313/ SCLK AD5323*
(DAC 2) SYNC LDAC SDO
AD780/REF192 WITH VDD = +5V
AD5303/ AD5313/ AD5323
VREFB GND VOUTB
R2 51.2k
DIN
Figure 43. Coarse/Fine Adjustment
AD5303/ AD5313/ AD5323* SCLK
(DAC N) SYNC LDAC SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. Daisy-Chain Mode
-16-
REV. 0
AD5303/AD5313/AD5323
t1 SCLK t8 SYNC t6 t5 DIN DB15 INPUT WORD FOR DAC N SDO UNDEFINED DB15 INPUT WORD FOR DAC N DB0 DB15 INPUT WORD FOR DAC (N+1) DB0 DB0 t15 t3 t4 t2 t14
SCLK t13 SDO VIL t12 VIH
Figure 45. Daisy-Chaining Timing Diagram
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5303/AD5313/AD5323 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5303/AD5313/AD5323 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the AD5303/AD5313/AD5323. The AD5303/ AD5313/AD5323 should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
The power supply lines of the AD5303/AD5313/AD5323 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
REV. 0
-17-
AD5303/AD5313/AD5323
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16)
0.201 (5.10) 0.193 (4.90)
16 9
0.177 (4.50) 0.169 (4.30)
1
8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19)
0.256 (6.50) 0.246 (6.25)
0.0256 SEATING (0.65) PLANE BSC
8 0 0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-18-
REV. 0
PRINTED IN U.S.A.
C3448-8-4/99

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